PLCcore-9G20
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Developing modern and sophisticated control systems
requires versatile, interdisciplinary know-how. This does not only involve
hardware and application development. In fact, operating system adaptations, the
connection of communication and field- buses as well as data exchange between
processes running in parallel become necessary. By applying the PLCcore-9G20 as
PLC kernel in user-specific controls this development effort can be
minimized.
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Main Features of PLCcore-9G20 |
| PLCcore Firmware |
IEC61131-3 runtime kernel pre-installed
Shared process
image
CiA302/314 compliant CANopen manager
Customizable I/O
driver
Program download via Ethernet or CANopen |
| Controller |
Atmel® AT91SAM 9G20,with ARM 926EJ-S Core, 32-bit |
| System Clock |
440MIPS at 400MHz |
| RAM (default/max) |
32/64MiB SDR-SDRAM |
FLASH
(default/max) |
16/64MiB NOR, 16-bit data-bus |
| On-board Peripherals |
DMA, MMU, hardware watchdog, temperature sensor, RTC |
| Interfaces |
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| Fast Ethernet |
1x 10/100Mbps, on-board PHY |
| CAN |
1 |
| UART |
4 |
| USB |
2x USB 2.0 host, 12Mbps full-speed
1x USB 2.0 device, 12Mbps
full-speed |
| SPI/I2C |
1 only with FPGA Firmware / 1 |
| Mass storage |
MMC/SD-card signals on board-to-board connector |
| FPGA |
Lattice ECP2-6 |
| Others |
SSC |
| Operating Conditions |
Temperature: -40°C…+85°C
Humidity: 10-90% RH,
non-condensing |
| Power Supply |
3.3V +/- 5%, 1A max. |
Dimensions/
Weight |
78 x 54 x 7,5 (L x W x H in mm),
20g |
| Board-to-board connector |
2x 50 pin header socket, 1.27 mm pitch |
| Available on
board-to-board connector |
CAN, USB device, 2 USB host, I˛C,
2 SD-card, Ethernet,
19 digital input lines, 8 digital output lines, 3 analog input lines, 4
PWM/DIO, 4 Timer/Counter/DIO |
| RoHS compliant |
yes |
| Operating System |
Linux |
Integrated Development
Environment
(IDE) |
Pre-integrated Eclipse-based IDE with GNU C/C++ tool chain,
source- and assembly-level debugger
IEC 61131-3 IDE (OpenPCS) with SYS TEC
vendor extensions |
| Complementary Middleware |
CANopen® Protocol Stack Source Code
Ethernet POWERLINK
Protocol Stack Source Code |
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